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Hardware Modelling

Module name (EN):
Name of module in study programme. It should be precise and clear.
Hardware Modelling
Degree programme:
Study Programme with validity of corresponding study regulations containing this module.
Electrical Engineering, Master, ASPO 01.10.2005
Module code: E913
Hours per semester week / Teaching method:
The count of hours per week is a combination of lecture (V for German Vorlesung), exercise (U for Übung), practice (P) oder project (PA). For example a course of the form 2V+2U has 2 hours of lecture and 2 hours of exercise per week.
2V+2P (4 hours per week)
ECTS credits:
European Credit Transfer System. Points for successful completion of a course. Each ECTS point represents a workload of 30 hours.
5
Semester: 9
Mandatory course: yes
Language of instruction:
German
Assessment:
Written examination

[updated 12.03.2010]
Applicability / Curricular relevance:
All study programs (with year of the version of study regulations) containing the course.

E913 Electrical Engineering, Master, ASPO 01.10.2005 , semester 9, mandatory course
Workload:
Workload of student for successfully completing the course. Each ECTS credit represents 30 working hours. These are the combined effort of face-to-face time, post-processing the subject of the lecture, exercises and preparation for the exam.

The total workload is distributed on the semester (01.04.-30.09. during the summer term, 01.10.-31.03. during the winter term).
60 class hours (= 45 clock hours) over a 15-week period.
The total student study time is 150 hours (equivalent to 5 ECTS credits).
There are therefore 105 hours available for class preparation and follow-up work and exam preparation.
Recommended prerequisites (modules):
None.
Recommended as prerequisite for:
Module coordinator:
Prof. Dr. Volker Schmitt
Lecturer:
Prof. Dr. Volker Schmitt


[updated 12.03.2010]
Learning outcomes:
This course provides students with a comprehensive introduction to the hardware description languages VHDL and VHDL-A. Combined with the extensive practical training in the use of typical software tools, students will be able to work independently to develop complex circuits and systems.

[updated 12.03.2010]
Module content:
- Hardware description languages, VHDL, Verilog, SystemC, VHDL-A, text editors,  
  circuit diagram editors
- Modelling digital systems with VHDL: Scope, basic structures, properties,  
  structure of VHDL models
- Language elements, declarations, object classes, entities, architectures,  
  processes, procedure functions, packages, blocks, concurrent and sequential  
  commands, code execution, time models, libraries
- Structured designs, hierarchy, synthesis
- Modelling analogue systems with VHDL: Scope, basic structures, properties,  
  model structure
- Lab course: Describing, simulating and synthesizing systems and circuits using  
  VHDL and VHDL-A

[updated 12.03.2010]
Teaching methods/Media:
Overhead transparencies, handouts, PC and video projector

[updated 12.03.2010]
Recommended or required reading:
Leibner, P.: Rechnergestützter Schaltungsentwurf; Krehl, Münster, 1996
HERTWIG, A.; BRÜCK, R.: Entwurf digitaler Systeme; Hanser-Verlag; ISBN 3-446-21406-2
SIEMERS, Chr.: Hardwaremodellierung; Hanser-Verlag; ISBN 3-446-21361-9
Lehmann; Wunder; Selz: Schaltungsdesign mit VHDL; Franzis-Verlag, 1994
BÄSIG, J.: Entwicklung digitaler Systeme mit VHDL; Eigenverlag; ISBN 3-00-005081-7
TEN HAGEN, K.: Abstrakte Modellierung digitaler Schaltungen; Springer Verlag;
REICHARDT, J.; SCHWARZ, B.: VHDL-Synthese; Oldenbourg Verlag; ISBN 3-486-25128-7
BHASKER, J.: Die VHDL-Syntax; Prentice Hall Verlag; ISBN 3-8272-9528-9


[updated 12.03.2010]
 
[Fri Nov 22 00:30:48 CET 2024, CKEY=eha, BKEY=em, CID=E913, LANGUAGE=en, DATE=22.11.2024]